A PLL circuit is a circuit wherein the oscillation frequency of a voltage-controlled oscillator is varied to adjust the phase so that the oscillation frequency may be locked at a target frequency. The PLL circuit occasionally falls into a state called deadlock due to, for example, a deviation between the operating frequency range of the voltage-controlled oscillator and that of the frequency divider. Such deadlock is caused due to disconnection of the loop in the PLL circuit when the frequency divider becomes unable to lock the output signal from the voltage-controlled oscillator.
The following techniques have been known as measures against the deadlock of a PLL circuit.
(see, e.g., Japanese Laid-open Patent Publication No. 2006-157630)
(see, e.g., Japanese Laid-open Patent Publication No. 11-8551)
(see, e.g., Japanese Laid-open Patent Publication No. 2006-174358)
(see, e.g., Japanese Laid-open Patent Publication No. 10-173520)
Japanese Laid-open Patent Publication No. 2006-157630 discloses a method of releasing a PLL circuit from deadlock. The technique disclosed in Japanese Laid-open Patent Publication No. 2006-157630 is based on the presupposition that when the PLL circuit is to be released from deadlock, the frequency-divided signal output from the frequency divider is fixed at a high or a low level. Depending on the operation of the frequency divider that failed to lock, however, the frequency-divided signal from the frequency divider in deadlock is not always fixed at a high or a low level, and in such case, a problem arises in that the frequency divider is unable to recover from the deadlock.